New boost type single phase inverters for photovoltaic applications with reduced device count

In recent years, single-stage boost inverters with common ground have shaped the inverter markets due to the many benefits associated with these types of inverters, including their high efficiency, single control scheme, and integrated boost converter. A new boost-type inverter that utilizes a common ground and has fewer switches is proposed in this article. It uses two DC-link capacitors connected in parallel and discharged independently while being charged simultaneously. The voltage for the positive and negative half cycles is supplied by the capacitors located at the top and bottom of the circuit, respectively. In addition, a comparison is made between the proposed circuit and the boost inverter already in use in the literature. Using PLECS as the computing software, the efficiencies are determined depending on the various percentages of output power. To validate performance, present experimental data, and attain the best possible efficiency of 97%, a 400 W prototype model is constructed. In addition to that, the breakdown of the costs is shown.


Introduction
In grid-connected transformer-less photovoltaic (PV) inverters, leakage current is one of the most important problems that might arise.This is because of the high-frequency commonmode voltage and the potential-induced deterioration (PID) polarization effect [1].For singlephase applications, the conventionally available two-level full-bridge inverter is the most common type of photovoltaic inverter employed.Common mode voltage and leakage current, on the other hand, provide substantial challenges [2][3][4].
Recent studies reveal that the common ground type (CGT) inverter could suppress the leakage current due to the direct connection between the grid and the PV panel's negative terminals.However, several single-stage transformer-less CGT-based inverter topologies are well reported in [5][6][7].To develop the inverter with its four switches, the two boost converters must first be linked at each end of the DC source terminals [6].
In addition, this topology requires two inductors, which, as a result of the predetermined dead time, causes the production of a greater amount of electromagnetic interference.By replacing the inductor with a coupled inductor, the topology explained in [7] improves the structure presented in [6].A high voltage dependent on the turn ratio is generated by the coupled inductor, which also serves to dampen the output ripples.However, the same issue persists here, which makes tracking the maximum power point in PV applications even more difficult.The integrated boost and full bridge inverter structures are presented in [8].Although this topology eliminates cross-over distortion, it suffers from high voltage stress on the DClink capacitor and switching loss of full bridge inverters.A new half-bridge inverter-based topology with the integration of a boost converter is presented in [9], and this topology has one high switching frequency switch for each half cycle.Although the topologies described above are appropriate for PV applications, the leakage current is still a little high.Further, the CGT is a good choice to suppress the PID effect.
Fig 1(A)-1(D) depicts the well-known three-level inverter topologies with a common ground feature.The common ground is achieved by inserting an additional capacitor (acting as a virtual DC source) in the H-bridge inverter shown in Fig 1(A) from [10].Further, this topology does not have the boosting ability, and the front-end DC-DC converter is included in the circuit to boost the input voltage.In addition, the presented DC-DC converter suppresses the inrush current by using the boost converter inductor, called the soft charging method.The topology depicted in Fig 1(B) and described in [11,12] is an improved version of the structure given in [10] with one capacitor and diode removed.
Nevertheless, the topologies [11,12] have the same structure, except that the structure given in [10] cannot feed reactive power into the grid, and the capacitor acts as a virtual DC source.By eliminating the front-end DC-DC converter and the inductor, an integrated H-bridge inverter with five switches is presented in [13], as shown in Fig 1 positioned in such a way as to produce boosting voltage with the assistance of one additional switch.As reported in [14], a recently proposed CGT topology with four switches and one capacitor lacks a boosting feature, as depicted in Fig 1 (D).In addition, this topology requires a capacitor with a voltage rating three times that of the grid voltage and a high inductance value.Further, the input voltage must correspond to the grid voltage.However, the previously stated single-phase, single, and double-stage inverter topologies have garnered substantial attention, and research and the development of novel techniques are ongoing.

(C). The boosting inductor is
In this regard, this article proposes a new single-stage boost inverter with common ground.The proposed topology provides a low leakage current with the same components as a conventional two-stage single-phase inverter.It uses a pair of parallel-connected DC-link capacitors that are charged simultaneously and discharged independently.The capacitors at the top and bottom of the circuit, respectively, supply the voltage for the positive and negative half cycles.Furthermore, a comparison is presented between the boost inverter that is currently in use in the literature and the suggested circuit.PLECS (a software tool for system-level simulations of electrical and electronic circuits) calculates the efficiency based on different output power percentages.A 400 W prototype model is constructed to verify performance, show experimental results, and achieve the highest possible efficiency of 97%.Furthermore, the breakdown of costs is provided.
The rest of the manuscript is organized as follows: Section 2 presents the proposed boost inverter, a description of the operating principle, and its pulse generation scheme.Section 3 presents an analysis of the power loss calculation.The proposed scheme is compared with more modern transformer-less three-level inverter topologies in Section 4. Section 5 shows that the proposed topology can be extended for a common ground connection for two DC sources.In Section 6, simulation and experimental results and discussion are provided.Section 7 concludes the work presented.) is connected to the cathode of the diode, while the other end is connected to the switch S 1 source terminal.The capacitor (C 2 ) is connected between the switches S 1 and S 2 .The switches S 3 and S 4 form the half-bridge module, and both are turned on and off in a complementary manner.

Principle of operation
In mode (+v in +v L ), shown in , the switch S 1 is closed, and the capacitor C 2 supplies the load through switch S 4 .The load output equation is v o = v C2 , and the inductor is charging, as given in (3).
In modes (freewheeling) and (+0 v in ), shown in Fig 3(D)-3(E), the switch S 1 is open, and the inductor current charges the capacitors C 1 and C 2 , and the switch S 2 will be conducted to provide the freewheeling path for the load.The load output equation is v o = 0, and the inductor is charging, as given in (4).
However, in these modes, the output voltage will be zero.Table 1 summarizes the switching sequence of the proposed boost inverter.
The voltage boost factor of the proposed inverter relies on the duty cycle of the switch S 1 , which is determined by (5).

D ¼ MjsinðotÞj ð5Þ
The voltage across the DC-link capacitors, C 1 =C 2 , is derived as follows: The calculated minimum capacitance of the capacitors primarily depends on the maximum power transfer, v o , switching frequency, and the maximum allowable capacitor ripple voltage.The approximate value of the capacitors can be obtained by multiplying the calculated minimum capacitance by the operating frequency as given in (7).
where P o is the output power and f sw is the switching frequency.Due to the capacitors' low equivalent series resistance, inverter operation and experimental validation typically require a higher capacitor value than the estimated one.Similarly, the inductor selection is the same as the boost converter, but it is designed in the DCM mode, and the critical inductance (L Cric ) value is eight.However, modest changes must be made in practical implementations.Because of the exceptionally low equivalent series resistance of the capacitors, the capacitor value should usually be more than the estimated value during inverter operation and experimental validation.Similarly, the selection of the inductor is identical to that of the boost converter.Still, it is designed in DCM mode, and the critical inductance (L Cric ) value is calculated as follows:

Pulse generation scheme
The pulse generation scheme for the proposed topology is shown in  S 1 and S 2 are operated at a high frequency.The pulses are obtained as expressed in ( 9) and (10).

Power loss analysis
The switch, Infineon IGBT (IGB30N60T), with an anti-parallel diode switch datasheet, is used to calculate the power loss of the switches.The individual component's power loss breakdown using the PLECS calculated is depicted in Fig 5(A).In the simulation, as discussed earlier, the capacitor loss is lower than the switching losses.Switches S 1 and S 2 have a higher loss due to operating at a higher switching frequency of 20 kHz, but switches S 3 and S 4 operate under fundamental switching frequency with low power losses.
Sensing the rising and dropping edges of the voltages throughout a simulation period (t s ), the number of switching events n may be computed.Further, the peak current and voltage may also be monitored.The datasheet describes the switching energy required to determine the average turn-on and turn-off loss of the power switch, as shown in (11).
The current and peak voltage at the nth rising and falling voltage edges are i peak (n) and v peak (n), respectively.When the power switch is on and off, the peak voltage and current are the switching energy functions f Eon and f Eoff .The power switch' average conduction loss is given in (12).
where i c and v CE are the collector current and emitter-collector voltage, respectively.

Comparative study with modern transformer-less three-level inverter topologies
The proposed scheme is compared with more modern transformer-less three-level inverter topologies in Table 2. Reactive power control becomes harder with the topology presented in [4] due to the increasing number of components.Buck and boost are constructed utilizing more components in [5].Additionally, the topology makes use of three inductors, which exacerbates the issue of electromagnetic interference (EMI).In [6], it is explained how to increase voltage with a common ground by using two capacitors and six switches.However, there is a commonality among the aforementioned topologies and an increasing number of passive or active devices.The dual boost inverter topology also referred to as the split inductor typetopology, was introduced in the studies presented in [7][8][9]15].Comparing these topologies to the current topology, fewer components are used.Unfortunately, two magnetic components are needed, which exacerbates the EMI issue and power losses.A current presentation of the virtual DC source-based topology may be found in [10][11][12].Except for the number of devices, these topologies functioned according to the same idea.Five switches are used in these common ground type topologies.Further, these topologies are separate from the single-stage operation, i.e., these topologies needed separate DC-DC boost converters to boost the input voltage.The single-stage boost inverter topology is presented in [13], where the boost converter is integrated with an h-bridge inverter.Still, this topology switch count is high compared to the proposed topology.In [14], the topology does not have a boosting ability.Even though one capacitor and one diode are additionally required in the proposed topology, the advantages are: (i) additional capacitor loss is less than the switching loss, and (ii) it does not require additional driver circuits.

Extended dual source structure
The proposed topology can be extended for a common ground connection for two DC sources, as depicted in Fig 6(A) and 6(B).Both ends of the grid are connected to the negative terminals of the two DC sources.Existing topologies in the literature introduced a single DC source connection and did not show source extensions.However, only two DC sources can be connected to a common ground in the proposed topology.If the number of DC sources increases, the common ground feature will remain the same for the two DC sources.
As depicted in Fig 6(A), the number of switches for each unit is reduced to three, and the zero state is achieved by connecting S 31 and S 32 since all capacitors will maintain the same voltage.If one of the sources fails, it will be difficult to obtain the zero state and regulate the voltage across the capacitor of the failed DC source unit; therefore, it is preferable to disconnect both sources from the grid if one source fails.To address this issue, the second configuration of    At a frequency of 20 kHz, switch S 1 charges the inductor to 100 V, which is then discharged to the capacitors at a modulation index of 0.8.To provide the positive cycle, the switch S 3 is turned on, and the voltage across the load will be 200 V. Fig 9(A) depicts the output voltage and current of the proposed inverter with a load value of 50+j50, a lagging power factor of 0.95, and a maximum load current of 3.0 A (i rms =2.10 A).The reactive power should be controllable for most inverter applications with a lagging power factor.Changing the power factor from 0.95 to 0.85 demonstrates that the proposed inverter topology can function with a lagging power factor.The measured waveforms are depicted in These measured values demonstrate that the proposed inverter increases the input voltage by a factor of two when the modulation index is 0.8.In addition, this design controls all four switches with a single pulse generating technique, i.e., it does not require an additional pulse generator for boost operation, enhancing its efficiency.Another crucial validation that must take place is a sudden change in the input, after which the switched/boost inverter must continue to operate and provide the same output voltage boosting ratio for a fixed duty cycle/modulation index.By increasing the input voltage of the suggested inverter from 75 V to 100 V, it was also tested.On the other hand, in the experimental setup, the direct DC source is used as the input rather than the PV, and MPPT tracking is not validated in this study.As can be seen in Fig 12, the LCL filter is placed in the path that runs between the proposed inverter output (v inv ) and the grid (v g ).A few assumptions are made to design the LCL filter, including setting the value of the lower LCL capacitor to three and assuming that the ripple attenuation (ΔR Iatt ) is 20%.The LCL filter design values are given in Table 3 for 400 W output power with a fundamental frequency (f f ) of 50Hz.

Simulation and experimental results and discussion
where Z b denotes the base impedance, L c denotes the inverter side inductance, C max denotes the maximum allowed capacitor value, C f denotes the filter capacitance, L g is the grid side inductance, and r is a function of the ripple attenuation.The LCL filter components value has been calculated as given below   The transfer function of the LCL filter is given in (16), and its corresponding bode plot is shown in Figs 1 and 2(B).
The proposed inverter is connected to the grid, and the corresponding inverter voltage, grid, and grid current are shown in Fig 13 .The peak voltage of the grid is 160 V, equal to ~110V, and the grid current is also shown.
Furthermore, the proposed topology's performance when connected to the grid under different power factors i.e., unity power factor, 0.71 lagging and leading power factor conditions is tested and the respective experimental results are shown in Fig 14(A)-14(C).The response while varying the grid reference (i g, ref ) from 1.5 A to 3A is depicted in Fig 14(D).
In Table 4, a cost comparison is made between the proposed topology and existing singlestage, single-phase boost inverter topologies [10][11][12][13][14].For the switches, ratings for 600 V are considered for all topologies, while the topology specifications determine the remaining passive components.The data in Table 4 confirm that the proposed topology costs less than the other alternative topologies.
Due to the reduced number of switches and gate drivers, the proposed inverter has a low cost.The efficiency of the proposed topology is computed with the PLECS simulation tools and measured with the experimental setup for resistive load, as shown in Fig 15 .The power quality analysis of the proposed topology is carried out in the MATLAB simulation as can be seen from Fig 16, the voltage THD (V THD ) and current THD (I THD ) values of the proposed topology after the LCL filter while injecting the power to the grid is 2.25% and 1.57% which is within the limits of IEEE 519 standard for THD.
The simulated efficiency is 93.85%, while the actual efficiency is 92.2%.In addition, the maximum efficiency achieved in simulation is 98.15%, whereas the measured efficiency is ~97% for an output power of 400 watts.

Conclusions
The paper presented a novel topology for single-phase, single-stage boost inverters, including a shared ground.In contrast to the topologies currently in use, the proposed topology employs a single diode and capacitor, reducing one switch along with its associated gate driver circuit.The extended structure demonstrates that the dual source is dual grounded, which presents a notable benefit of the suggested structure.This paper clarifies the design of the LCL filter utilized in the grid-tied system and verifies that the suggested topology is appropriate for reactive power regulation.Nevertheless, the efficiency of the inverter's design was upheld at a reduced cost compared to alternative topologies.The suggested topology is most appropriate for the utilization of photovoltaic systems, particularly in the context of rooftop PV installations with limited scale.The experimental findings validate this claim, and the internationally accepted benchmark for efficiency was quantified and recorded.

Fig 2
Fig 2 depicts the circuit diagram of the proposed topology, which consists of two capacitors, four switches, one diode, and one inductor.One end of the inductor is connected to the source voltage (v in ), and the other is connected between the diode anode and the drain terminal.As depicted in Fig 2, the capacitor (C 1) is connected to the cathode of the diode, while the other end is connected to the switch S 1 source terminal.The capacitor (C 2 ) is connected between the switches S 1 and S 2 .The switches S 3 and S 4 form the half-bridge module, and both are turned on and off in a complementary manner.

Fig 3
Fig 3 shows the five modes of operation of the proposed topology.They are described as follows: In mode +v C1 , shown in Fig 3(A), the switch S 1 is closed, and the capacitor C 1 supplies the load through the switch S 3 .The load output equation is: v o = v C1 and the inductor is charging as given in (1): Fig 3(B), the switch S 1 is open, and the inductor current charges the capacitors C 1 and C 2 and supplies the load through switch S 3 .The load output equation is v o = +v m +v L , and the inductor is charging, as expressed in (2).

Fig 4 .
The level-shifted triangular pulse width modulation scheme is used (v tri ) as a carrier signal compared with the reference signal (v ref ) to generate the required pulses.During pulse generation, the switches S 3 and S 4 operate at the fundamental switching frequency, i.e., 50 Hz, but the switches S 1 and S 2 are complementary switches that operate at high frequency, i.e., 20 kHz.It confirms that the proposed topology does not require additional pulses to boost the input voltage since switches

Fig 6 (
B), which is an extension of the configuration shown in Fig 2, is recommended.Since the zero states can be reached by turning on the switches S 21 and S 22 , in this configuration, if either source fails, the other DC source will maintain the DC link voltage by adjusting the boost switch's duty cycle to match the grid voltage.

Fig 7 (
Fig 7(A)-7(F) show the simulation results of the proposed topology where the input voltage is kept at 100 V, and the corresponding output voltage (v o ) is 180 V (as shown in Fig 7(A)) for a

Fig 8 .
Fig 8. Hardware setup of the proposed topology.https://doi.org/10.1371/journal.pone.0304463.g008 The measured voltage and current waveforms are shown in Fig 10(A), and the corresponding changes in the capacitor and inductor are shown in Fig 10(B).As shown in Fig 10(B), the inductor current and capacitor voltages oscillate to the maximum of 220 V capacitor voltage, and the maximum inductor current reaches 18 A.This occurs when there are sudden changes in the input.Fig 10(C) depicts the output voltage and current, which uses a reduced modulation index of 0.5.While decreasing the modulation index, the

Table 4 . Cost comparison of the proposed topology with the existing topologies for v o =200 v.
TQ denotes the total quantity, and TP denotes the total price. https://doi.org/10.1371/journal.pone.0304463.t004